Re: Question: related to System bus bandwidth

[John R Pierce <pierce@scruznet.com>]

At 12:52 PM 11/15/96 -0800, subbarao@rd.smos.com (Arumilli Subbarao) wrote:
>For PCI we can plug Logic analyzer and observe the transactions. (basically
>using one pci slot).  But how do we do this for processor-memory system bus. We
>cant attach logic analyzer to processor pins or chipset pins (because very 
>narrowly soldered). Is there any way.

Hmm.  Well, one suggestion might be to probe the CS and WR lines on the
cache SRAM as well as RAS, CAS, and WE on a DRAM simm.  This would let you
track the number and type of memory cycles (i.e. cache read, cache write,
and main memory read/write) as well as the lengths of main memory bursts...

If this is a pentium, in the usual ZIF socket, you may be able to construct
a 'riser' socket from a AUGAT style wirewrap socket, and probe pins off of
this...

Alternately, 'lbw's ("Little Blue Wires") soldered to the processor socket
pins on the bottom of the motherboard may be of some use? 

-jrp
(who's really a software guy but had to do similar things in the past)
ìÜ