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Re: Question: related to System bus bandwidth
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Re: Question: related to System bus bandwidth
- From: gsc@Traveller.COM (GSC)
- Date: Fri, 15 Nov 1996 18:11:47 -0600
- Cc: pci-sig@znyx.com
- Resent-Date: Fri, 15 Nov 1996 18:11:47 -0600
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"x9oaX1.0.U56.xVGZo"@dart>
- Resent-Sender: pci-sig-request@znyx.com
>
>
>Hi
>
>I have a question regarding the calculation(observation) of the bus bandwidth.
>
>For PCI we can plug Logic analyzer and observe the transactions. (basically
>using one pci slot). But how do we do this for processor-memory system bus. We
>cant attach logic analyzer to processor pins or chipset pins (because very
>narrowly soldered). Is there any way.
>
>We want to profile the system bus utilization. Any pointers are welcome.
>
>Thanks
>SUbbarao.
>
>
>
>
We are able to probe 208-PQFP's with with very small clips from Emulation
Technology, Inc. They also have adapters which provide an ordinary square
post for every pin of such a large chip. In my experience, both are some
trouble to use; but it may be inevitable for such a fine pitch. The small
clips are on page 110 of their 1996 Interconnect Solutions catalog.
Their phone number is 408-982-0660, fax 408-982-0664
Best Regards,
Michael Lee (speaking for myself)
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