FW: how do we write a single byte in the CSR...

["Taylor, Mike" <mike@buntypost.dundee.ncr.com>]

 ----------
From: 	pci-sig-request[SMTP:pci-sig-request@znyx.com]
Sent: 	21 November 1996 17:43
To: 	Mailing List Recipients
Subject: 	how do we write a single byte in the CSR...

part1 (text/plain)
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> Method #2 uses IO space C000-CFFF. Bits 11-8 select the PCI device (1   
of
> 16), bits 7-2 select a DWORD in the device's configuration space. IO
> accesses are therefore to C0xx, C1xx, thru' CFxx. This problem exists,   
a
> well known graphics card BIOS attempts Config #2 cycles and interferes   
    

> with a proprietary card in our system.
> Mike.
>  ----------
> From: 	pci-sig-request[SMTP:pci-sig-request@znyx.com]
> Sent: 	20 November 1996 08:23
> To: 	Mailing List Recipients
> Subject: 	Re: how do we write a single byte in the config. registers?
>
> > Beware of config. method #2. If your host chipset does not support
> method
> > #2, Triton family for example, then the accesses appear on the ISA   
bus
>
>
> > and ISA cards can react to the aliases of the config addresses. e.g.   
    

> C200
> > can be seen as x200.
>
> Ah, but isn't the port in question always X0XX?  [I don't have my PCI
> references handy to recall the details here...]  If so, that shouldn't   
be
> a
> problem, as addresses with 00 in bits 8,9 are reserved for the
> motherboard and
> a PCI motherboard will decode bits 10-15=0 before enabling motherboard   
    

> IO...
>
>  -jrp

I understood that the processor's byte enables would be passed by the   
host
bridge to the PCI bus directly. This enables us to do read or write   
single
byte configuration cycles. Actually our first doubt was, how the host   
bridge
would generate the byte enables for reading/writing different bytes of a   
dword
individually.

As mike opines, I too feel that the read/write may appear in the ISA bus   
if
more than 256 address locations are used in the configuration space of   
the
second method and if the second method is not supported by the bridge.   
But I
also wonder, what is the space above 256 locations is used for in the   
second
configuration mode. Thanx.

 -Jasper

The first 256 locations are the registers on Device 0, the next 256 are   
on Device 1 etc up to 16 devices per bus. (Cdxx where d selects the   
device, xx selects the register).
Mike.
3xh