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MRM, MRL, MWI question



1) What is the required response by a target (i.e. system memory) if a 
PCI Master issues a MRM (or MRL) command with an address which is 
not aligned to a cacheline boundary?  Also what is the real world response
to this situation (i.e. what do various host bridges actually do if the start
address or end address of a burst is not cacheline aligned)?

2) The PCI spec (pg 23) requires that MWI's are aligned to cacheline boundaries.
What happens in the real world if an MWI is issued, but the start or end of
the burst is not cacheline aligned?

  holeman
  ____________________________________________________________________________

  Jim Holeman                                          Tandem Computers, Inc.
  (512) 432-8755 (fax 8247)                            14231 Tandem Boulevard
  holeman@isd.tandem.com                               Austin, Tx   78728-6699

  "A gentle answer turns away wrath"
<\J