Re: MRM, MRL, MWI question

["Monish Shah" <monish@hpfcmss.fc.hp.com>]

On Nov 22, 11:38am, Jim Holeman wrote:
> Subject: MRM, MRL, MWI question
> 1) What is the required response by a target (i.e. system memory) if a
> PCI Master issues a MRM (or MRL) command with an address which is
> not aligned to a cacheline boundary?

The read is required to work correctly.  The use of MRM and MRL does not
represent a commitment by the master.

> Also what is the real world response
> to this situation (i.e. what do various host bridges actually do if the start
> address or end address of a burst is not cacheline aligned)?

I don't know.  I would guess that they would start at the specified address
and prefetch ahead by whatever amount they normally prefetch by on the
specified command.

> 2) The PCI spec (pg 23) requires that MWI's are aligned to cacheline
boundaries.
> What happens in the real world if an MWI is issued, but the start or end of
> the burst is not cacheline aligned?

Based on some previous postings, I would expect typical desktop chipset
from Intel to work "correctly", i.e., it will work as if the write was MW
instead of MWI.  For server type systems, I wouldn't be surprised if the
cacheline that was written partially is trashed.

>   holeman
>   ____________________________________________________________________________
>
>   Jim Holeman                                          Tandem Computers, Inc.
>   (512) 432-8755 (fax 8247)                            14231 Tandem Boulevard
>   holeman@isd.tandem.com                               Austin, Tx
  78728-6699
>
>   "A gentle answer turns away wrath"

Monish Shah
Hewlett Packard
>°
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