Target Termination Rules

[Christian Huter <cmhuter@stud.ee.ethz.ch>]

I don't see why I have to stick to target termination signaling 
rule 3 (PCI Spec. v2.1, p.42), when I signal a disconnect and 
the master has its IRDY# signal already asserted. The current
data phase completes but according to rule 3 I have to keep
STOP# asserted until the master completes the last data phase
and the transaction by deasserting FRAME#. 

The reason I bother is that I must not rely on the master to
deassert its FRAME# signal on the first clock of the last data
phase. Therefore, if I don't want to violate rule 3, I must be
able to react to a PCI signal within one clock cycle (deassertion
of STOP# and DEVSEL# upon the deassertion of FRAME#). In all
other transactions I want to support in my target design in a
rather slow device I would not have to do that.

Question: Can anyone imagine any problems if I signal a disconnect,
	  when the master has its IRDY# already asserted, and 
	  blindly deassert STOP# and DEVSEL# on the second clock 
	  following the data phase terminated with a disconnect?  
 	  
Christian Huter
DTC