[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Detected Parity Error bits on multi-function devices
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Detected Parity Error bits on multi-function devices
- From: frank.story@tempe.vlsi.com
- Date: Wed, 27 Nov 1996 17:43:23 -0700
- Resent-Date: Wed, 27 Nov 1996 17:43:23 -0700
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"qQJ6a3.0.TB3.M1Edo"@dart>
- Resent-Sender: pci-sig-request@znyx.com
I have a corner case sort of a question about bit 15 in the
status register. This bit should be set whenever a parity
error is detected by a device.
The description I'm having trouble nailing down is the second
to the last paragraph of Section 3.8.1, which states in part
"Agents that support parity checking must always set the Detected
Parity Error bit in the Configuration Space Status register
(refer to Section 6.2.3) when a parity error is detected."
In the case of a multi-function device, each function has its
own status register with its own Detected Parity Error bit in
bit 15. Its pretty clear that any address parity error should
set bit 15 of the status register in each and every function.
Its not so clear that a data parity error should do the same.
I can't find a requirement that detection of data errors is
required by targets that are not selected. It seems more
intuitive that only the selected target would detect data
errors. Therefore, I believe that data parity errors should
set status bit 15 only in the target that returned DEVSEL#.
However, the way I read the spec, *all* targets should set
status bit 15 in the event of data parity errors. In terms
of the multi-function device, any data parity error should
set bit 15 of the status register in each and every function.
I do recognize the fact that this wouldn't affect the need
for a seperate status bit 15 for each function. The ability
of software to clear the status bits individually must be
preserved. I'm just not sure whether the set mechanism can
be common.
So, do I set bit 15 of all status registers on data parity
errors, or only on the selected target?
Thanks,
Frank
Frank Story frank.story@tempe.vlsi.com
VLSI Technology 602-752-6098
Computing Products Group
L è Ø