Re: CPU - PCI cycles

[Braun_Josef#Tel3805 <bj3805@denbgm31m.scnn1.msmgate.m30x.nbg.scn.de>]

Rafi Boneh <RAFIB@GILAT.MHS.CompuServe.COM> writes...
> I am trying to write a Win95 VXD for a PCI chip.
> I am using a PCI bus analyzer and trying to compare my code to what I see
> on the bus.
> It seems that there are some differences. For instance:
> *) I am writing twice the same LongWord to the same address, and I see
> only one single transfer transaction on the PCI bus.
> *) When I write two different LongWords to the same address, I again see
> only one single transfer transaction, with data equivalent to the second
> write.
> It seems like the host bridge "interprets" my commands, and decides
> itself that there is
> no sense in writing the same word to the same location twice, or writing
> different words to the same locations, and so on.
> I have my own reasons to do so (accessing command and control register on
> the chip).
>
> Dose some one have an idea how can I access the locations I want, in the
> sequence I want, or what limitations do I have one such operations?


jrp answered
> Um, presumably your chip's address space is marked
> non-prefetchable/non-cacheable??  only if memory is cacheable should what 
you
> see be taking place!!

I don?t think so!
A write to any location has to be ececuted regardless of whether the address
space is marked non pref or pref.

sep
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