Target Initial/Subsequential Latency

[Braun_Josef#Tel3805 <bj3805@denbgm31m.scnn1.msmgate.m30x.nbg.scn.de>]

With implementing the target latency requirements of a company proprietary
PCI design we from our point of view detected an inconsistency of the actual
specification.

A target that wants to fulfil the requirements of the actual spec has to 
transfer
the data within 16 clocks starting with frame for the initial data phase
and within 8 clocks starting at the end of the preceding data phase.

But the target has to fulfil this requirements regardless of when the
master is able to transfer the data indicated by asserting IRDY.
The master has to assert IRDY no later than 8 clocks after asserting FRAME
for the initial data phase and no later than 8 after the preceding data
phase for a subsequential transaction.

So for the initial transaction the target has a real chance to fulfil the
requirements because there are 8 clocks left to transfer the data.
But for a subsequential data phase the master might come at the
8. cycle and the target has to disconnect the transaction without
having a real chance to make it.

Any comments? Are all of you content with this implementation possibility?

sep
h(