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Re: Target Initial/Subsequential Latency
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Re: Target Initial/Subsequential Latency
- From: larky@anchorchips.com (Steven Larky)
- Date: Thu, 5 Dec 1996 09:11:51 -0800 (PST)
- In-Reply-To: <32A734BE@MSMGATE.M30X.NBG.SCN.DE> from "Braun_Josef#Tel3805" at Dec 5, 96 12:45:00 pm
- Resent-Date: Thu, 5 Dec 1996 09:11:51 -0800 (PST)
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"MxXn03.0.4C5.uCmfo"@dart>
- Resent-Sender: pci-sig-request@znyx.com
Braun_Josef#Tel3805 said:
>
> But the target has to fulfil this requirements regardless of when the
> master is able to transfer the data indicated by asserting IRDY.
Exactly! Reread the spec. The target should and must assert
TRDY unconditionally and without waiting for IRDY. The first cycle
that IRDY and TRDY are simultaneously asserted causes a data transfer.
So if both the target and the master follow the spec, and both happen
to assert on the 8th clock, data gets transfered, all is well, and no
one is happy. Why is no one happy? Because bus bandwidth was wasted.
--------------------------------------------------------
| Steven Larky |
| Principal Engineer |
| larky@anchorchips.com Anchor Chips Inc. |
| Phone: 619-676-6815 12396 World Trade Dr., Ste 212 |
| Fax: 619-676-6896 San Diego, CA 92128 |
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