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Re: Unused memory bars allowed
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Re: Unused memory bars allowed
- From: frank.story@tempe.vlsi.com
- Date: Thu, 5 Dec 1996 15:16:09 -0700
- Cc: pci-sig@znyx.com
- Resent-Date: Thu, 5 Dec 1996 15:16:09 -0700
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"8knJ4.0.J06.cdqfo"@dart>
- Resent-Sender: pci-sig-request@znyx.com
Not only allowed, but also being done in current implementations.
The PCI IDE specification does just exactly what you describe. It
provides for two *optional* base I/O registers for channel 0 at
10h & 14h, two *optional* base I/O registers for channel 1 at 18h
& 1Ch, then finally a base I/O register for bus mastering registers
at 20h. The IDE controller is allowed to be legacy only, which
means no channel 0 or channel 1 base I/O registers, but the bus
mastering I/O base register stays at 20h.
Frank
> Hello
> on a PCI interface chip I found the option to disable the first memory bar. The first bar points to some config registers which
> I don?t need. The second and third bars are used for memory or IO. Assunig that it is better not to claim system resources
> which a not really need I thought about disabling the first bar.
> But is it allowed to have empty bars in between and not only at the end ?
>
>
Frank Story frank.story@tempe.vlsi.com
VLSI Technology 602-752-6098
Computing Products Group
n 8 '