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Re: Some questions
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Re: Some questions
- From: Duane Clark <Duane.Clark@jpl.nasa.gov>
- Date: Fri, 06 Dec 1996 08:34:42 -0800
- Organization: Jet Propulsion Laboratory
- Resent-Date: Fri, 06 Dec 1996 08:34:42 -0800
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"OZ7b53.0.k4.cj4go"@dart>
- Resent-Sender: pci-sig-request@znyx.com
- Sender: dclark@jpl.nasa.gov
John R Pierce wrote:
>
> Most all PC (ie. pentium systems) won't generate burst reads, only
> burst writes. There's no guarantee that you won't get a target retry abort
> somewhere in the middle of that burst.
Yow!! This is a truly scary statement. I am new to PCI and was in the
process of a board design (for in-house use). The board is currently
planned to be used in a 166MHz pentium Compaq running Solaris X86. I
would be hard pressed to meet system needs without burst read
capability. So what is preventing this? Is it built into the bridge or
other hardware or a feature of the operating system or just what??? Do
other systems allow burst reads? Do I need to implement bus mastering?
If I do so, would the PC bridge allow burst writes to system memory?
Any enlightening info would be greatly appreciated.
--
-Duane
p 0