Unused memory bars allowed

["Gardiner C, BSHEPS" <CHARLES.GARDINER@S31.MCH1.x400.sni.de>]

Even if it is being done, I would interpret the spec. to mean that 
it is NOT allowed, or at the very least not intended. The 
penultimate paragraph in section 6.2.5.1 on page 197 says...

The first Base Address register is always located at offset 10h. 
The second register may be at offset 14h or 18h depending on the 
size of the first. The offsets of subsequent Base Address 
registers are determined by the size of previous Base Address 
registers.

Charles Gardiner
Design Engineer
Siemens-Nixdorf Informationssysteme AG
Munich, Germany

>> -----------------------------------------------

>Not only allowed, but also being done in current implementations.
>The PCI IDE specification does just exactly what you describe. It 
>provides for two *optional* base I/O registers for channel 0 at 
>10h & 14h, two *optional* base I/O registers for channel 1 at 18h 
>& 1Ch, then finally a base I/O register for bus mastering 
>registers 
>at 20h. The IDE controller is allowed to be legacy only, which 
>means no channel 0 or channel 1 base I/O registers, but the bus 
>mastering I/O base register stays at 20h.

>Frank

>> Hello
>> on a PCI interface chip I found the option to disable the first 
>>memory bar.  The first bar points to some config registers which
>> I don?t need. The second and third bars are used for memory or 
>>IO. Assunig that it is better not to claim system resources
>> which a not really need I thought about disabling the first 
>>bar.
>> But is it allowed to have empty bars in between and not only at 
>>the end ?
>> 
>> 


>Frank Story                    frank.story_tempe.vlsi.com
>VLSI Technology                602-752-6098
>Computing Products Group

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