RE: Some questions

["Kimmery, Clifford (FL51)" <kimmery@space.honeywell.com>]

Does this mean that most CPU-PCI bridges do not attempt to prefetch
unless the target address is known to be cacheable?

An agent can be prefetchable (no read side-effects) without being
cacheable (no potential for hidden changes).

Cliff Kimmery
Honeywell Inc.
kimmery@space.honeywell.com

>----------
>From: 	David O'Shea[SMTP:daveo@corollary.com]
>Sent: 	Friday, December 06, 1996 1:06 PM
>To: 	Mailing List Recipients
>Cc: 	daveo@corollary.com
>Subject: 	Re: Some questions
>
>
>>Duane Clark <Duane.Clark@jpl.nasa.gov> writes
>>> 
>>> John R Pierce wrote:
>>> > 
>>> > Most all PC (ie. pentium systems) won't generate burst reads, only
>>> > burst writes.  There's no guarantee that you won't get a target
>>> > retry abort somewhere in the middle of that burst.
>>> 
>>> Yow!! This is a truly scary statement. I am new to PCI and was in the
>>> process of a board design (for in-house use). The board is currently
>>> planned to be used in a 166MHz pentium Compaq running Solaris X86. I
>>> would be hard pressed to meet system needs without burst read
>>> capability. So what is preventing this? Is it built into the bridge or
>>> other hardware or a feature of the operating system or just what??? Do
>>> other systems allow burst reads? Do I need to implement bus mastering?
>>> If I do so, would the PC bridge allow burst writes to system memory?
>>
>
>>At 09:09 AM 12/6/96 -0800, John R Pierce wrote:
>>Well, basically, the pentium processor will only do burst reads on locations
>>that are cacheable.  This pretty much eliminates all forms of IO devices as
>>caching them would cause more problems than good.
>>
>>The best way to transfer data from a peripheral to main memory is with
>>busmastering.  You can in theory achieve 100Mbyte/sec, but
>>60-80Mbyte/sec are
>>probably more typical.
>
>Depending on one's definition of a burst, there is a slight correction
>to this
>with MMX technology P5 and P6 CPU's.  With the new processors, there is
>an 
>instruction that allows 64 bit reads and writes.  Previosly, this was
>limited
>to 32bits for uncached memory accesses.   So, if your definition of a
>burst
>is only 64bits of information ;-)   then the new MMX CPU's can burst a
>little.
>Otherwise, John is 100% correct.   In any case, you really need to
>implement
>bus mastering with P5 and P6 PC's because of the inability to do "real"
>bursted
>reads at all and in most cases writes as well.   (PC's can burst write
>sometimes 
>because the CPU to PCI bus bridge has posted write buffers.   While the
>Bridge
>waits for the PCI bus, the CPU can non-burst transfer over the CPU bus
>to the
>posting buffers of the Bridge.   Then the bridge bursts all of the data
>in the
>posted write buffers.    This cannot happen on reads because the CPU
>blocks
>waiting for the read data from each successive read.   The maximum
>individual
>read over the CPU bus from the CPU to bridge (uncached read) is 32bits
>(now
>64bits).
>
>So, better implement bus mastering.....
>
>-Daveo
>
>
t„s