Re: Some questions

["John R Pierce" <pierce@hogranch.com>]

Mark Gonzales <markg@scic.intel.com> writes...

> I don't know of any CPU-PCI bridge that will prefetch for a CPU read
> from the PCI bus. Most CPU-PCI bridges can be configured to prefetch for
> PCI bus master reads from cacheable system memory that lives on the CPU
> bus.
> 
> This is why it is essential to implement bus mastering for good PCI bus
> performance. Using CPU reads and writes to do I/O to PCI will give poor
> performance for your device, and it will usually slow down any other bus
> mastering PCI devices in the system.

actually, host WRITE performance to a PCI target is quite acceptable, I've seen
on the order of 60-80MByte/sec continuously for large transfers (100's of
kbytes to several megabytes) to various targets (mostly graphics cards, thats
what I deal with).  Its host READ performance thats quite limited.  (I'm
talking about reasonably fast pentiums (133, 166) with triton chipsets here).

-jrp
wL;