Re: Some questions

[Graeme Gill <graeme@digideas.com.au>]

> dclark@jpl.nasa.gov wrote:
> John R Pierce wrote:
> > 
> > Most all PC (ie. pentium systems) won't generate burst reads, only
> > burst writes.  There's no guarantee that you won't get a target retry abort
> > somewhere in the middle of that burst.
> 
> Yow!! This is a truly scary statement. I am new to PCI and was in the
> process of a board design (for in-house use). The board is currently
> planned to be used in a 166MHz pentium Compaq running Solaris X86. I
> would be hard pressed to meet system needs without burst read
> capability. So what is preventing this? Is it built into the bridge or

> Any enlightening info would be greatly appreciated.

You need a processor chip that supports multi-word reads at the
instruction level to get bursts to non-cachable regions. A processor
with a 64 bit word for instance, whould give you a burst of two
32 bit words. Something like an 80960 should give you bursts
of 4 32 bit reads, and a 29000 could give you even longer bursts.

You could try using floating point reads on the x86 processor familiy,
but the overall throughput may not be that good, since you have to
get the data out of the floating point registers.

A smart bridge chip could merge reads into bursts if you are
using a processor that can have more than one outstanding read
on its I/O bus. The question is, are there any processor chips
like that out there, and are there any matching bridge chips ?

	Graeme Gill.
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