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Latency Timer value of 0
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Latency Timer value of 0
- From: Joe Cowan <jpc@hpmckee.fc.hp.com>
- Date: Mon, 9 Dec 96 11:18:10 MST
- Mailer: Elm [revision: 70.85]
- Resent-Date: Mon, 9 Dec 96 11:18:10 MST
- Resent-From: pci-sig-request@znyx.com
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Greetings,
The PCI 2.1 spec states that the reset value for a programmable Master
Latency Timer (MLT) register is zero. However, I haven't found an
explicit statement of what behavior is required when the MLT is zero. I
would hope that a value of zero effectively disables the latency timer
function, allowing a device to do long bursts even when other devices
request the bus. Is this the case? Does the spec explicitly state
somewhere what the required behavior is?
Thanks,
Joe Cowan
*----------------------------------------------------------------------*
| JOE COWAN |
| System Architecture and Design Lab |
| Email: jpc@fc.hp.com Joe Cowan - MS B5 |
| Work: (+1) 970 229-2404 | (T)229-2404 Hewlett-Packard Company |
| Fax: (+1) 970 229-3197 | (T)229-3197 3404 East Harmony Road |
| Fort Collins, CO 80525 USA |
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