[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: Latency Timer value of 0
> The PCI 2.1 spec states that the reset value for a programmable Master
> Latency Timer (MLT) register is zero. However, I haven't found an
> explicit statement of what behavior is required when the MLT is zero. I
> would hope that a value of zero effectively disables the latency timer
> function, allowing a device to do long bursts even when other devices
> request the bus. Is this the case? Does the spec explicitly state
> somewhere what the required behavior is?
>
> Thanks,
> Joe Cowan
>
Joe-
LT value of zero should result in your master getting off the bus as soon
as possible after it's grant goes away. This may be
desired behavior in a system. This is not stated in the spec, but the spec
does not make any special case for "when the LT is 0, do this".
-Tom
--
Tom Hicks Fore Systems
Design Engineer 174 Thorn Hill Rd
Adapter Group Warrendale, PA 15086
thicks@fore.com
~ Ô Â