Re: SVGA cards on PCI and store gathering

["John R Pierce" <pierce@hogranch.com>]

> > Um.  Generally the host writes data into the video ram (which could be
DRAM,
> > VRAM, or other organizations such as RDRAM), then the video card repeatedly
> > fetches this to refresh the CRT display.
> 
> This raises another question. Since the CPU writes the data to the vram in a
series
> of single beat cycles, it could make a lot of sense for the host bridge to
support
> store gathering. We are currently trying to determine whether this
not-trivial feature
> is worth implementing in our design. Does anyone know if the Pentium Host
bridges support it (I
> know the PowerPC host bridge - mpc106 does) ?
> Also, do you know of any other compelling reason to implement it, other than
the graphic cards 
> non-burst data profile ?

Yes, the triton bridges used on most all modern pentium systems will merge
pending writes to consecutive locations into a burst.  Since the Pentium can
generate writes faster than the video boards can swallow them, this works quite
nicely.  Graphics driver software goes to some lengths to try and use DWORD
aligned writes to take full advantage of this.  Ditto, a hardware accelerator
will often be designed so that its registers are layed out in the order that
they are most likely to be written so that the host bridge can merge the
register writes into a burst.

Without bursts, single host->PCI transfers appear to mostly take 3 or 4 clocks
(assuming the target is ready).  This would limit the PCI bus to about
33-40Mbyte/sec.   Since the memory interface on many video cards can accept
data at upwards of 80Mbytes/sec, bursts are necessary. Ditto, graphics
accelerator command fifos can often accept data at speeds as high as
100Mbyte/sec or more.

I'm curious (I am a software guy, not a hardware guy)... Every time I've
observed a PCI bus (Triton based Pentium systems) with a logic analyzer, I've
seen at least one IDLE cycle between each complete transaction sequence.  Is
this required by the protocol or just sloppy implementation on the part of the
triton PCI bridge?

-jrp
‚XH