Re: SVGA cards on PCI and store gathering

[Noam Halevy <noamh@msil.sps.mot.com>]

Hi,

> I'm curious (I am a software guy, not a hardware guy)... Every time I've

You seem to know about hardware, far more than many hardware guys I know ...

> observed a PCI bus (Triton based Pentium systems) with a logic analyzer, I've
> seen at least one IDLE cycle between each complete transaction sequence.  Is
> this required by the protocol or just sloppy implementation on the part of the
> triton PCI bridge?

The idle cycle is probably due to the fact that the bridge is not capable of 
fast-back-to-back (FBTB) transfers .I'm not sure about the triton, since I'm in the 
PowerPC area, but every other bridge I surveyed In prepration for my design
(PPC to PCI bridge) could not generate FBTB, although, it could accept them.
I think that implementing FBTB complicate the PCI master state machine in a
nasty way, so most designers (me too probably :-<) prefer to take the performance
hit rather than risk bugs in their designs.

Thanks for your response !

Best regards,

Noam Halevy 

email: noamh@msil.sps.mot.com
Tel: 972-3-590534

                 MSIL 
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