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Re: SVGA cards on PCI and store gathering
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Re: SVGA cards on PCI and store gathering
- From: Tom Hicks <thicks@fore.com>
- Date: Tue, 10 Dec 1996 09:06:05 -0500 (EST)
- In-Reply-To: <199612101006.CAA25137@scruz.net> from "John R Pierce" at Dec 10, 96 02:06:05 am
- Resent-Date: Tue, 10 Dec 1996 09:06:05 -0500 (EST)
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"aVghf.0.F12.UuMho"@dart>
- Resent-Sender: pci-sig-request@znyx.com
>
> I'm curious (I am a software guy, not a hardware guy)... Every time I've
> observed a PCI bus (Triton based Pentium systems) with a logic analyzer, I've
> seen at least one IDLE cycle between each complete transaction sequence. Is
> this required by the protocol or just sloppy implementation on the part of the
> triton PCI bridge?
>
> -jrp
>
Yes, at least one idle cycle is required, unless the host bridge is set to
perform fast back-to-back transfers. But fast back-to-back transfers
are difficult because the bridge must know the target memory/io boundaries,
to avoid trying to do a back-to-back transfer to different targets. Further,
fast back-to-back transfers can only occur for writes (since reads require
a turnaround cycle between the last data transfer and the address cycle).
-Tom
--
Tom Hicks Fore Systems
Design Engineer 174 Thorn Hill Rd
Adapter Group Warrendale, PA 15086
thicks@fore.com
„