Re: SVGA cards on PCI and store gathering

[havard@brooktree.com (havard scott)]

> From pci-sig-request@znyx.com Tue Dec 10 04:12:04 1996
> 
> I'm curious (I am a software guy, not a hardware guy)... Every time I've
> observed a PCI bus (Triton based Pentium systems) with a logic analyzer, I've
> seen at least one IDLE cycle between each complete transaction sequence.  Is
> this required by the protocol or just sloppy implementation on the part of the
> triton PCI bridge?
> 
> -jrp
> 

Yes, an IDLE or turnaround cycle is required between bus cycles. 
However, there is an optimization that is possible.  If both the 
target and the host (or slave and master) support something called
"fast back-to-back" transfers, and the master knows that it is sending
consecutive write commands to the same slave, then it is possible
to eliminate this idle clock. Obviously, I can't say why it wasn't
done in your situation. I am guessing that the Triton chip supports
it.
 ‡ìÜ