Burst Write Transfers from PC Host's Perspective

[Brian Carlson <bcarlson@dnaent.com>]

Hello, 

Does PC host software have control over when burst transfers are
used to address a PCI memory-mapped device or is this handled
automatically in hardware (keying off of sequential address accesses)?  

I have a device on my board that will be mapped into the PCI memory map
with which I would like to be able to take advantage of burst
write transfers. The device only requires a single memory
address decode for access (it looks like a FIFO).  If I am going to send a 
block of data to it, does the software have to address sequential 
addresses or can it just write to a single address and get the timing
benefit of the burst mode transfer?

Thanks,
Brian
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| Brian Carlson         | mailto://bcarlson@dnaent.com  |
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