Re: Burst Write Transfers from PC Host's Perspective

["John R Pierce" <pierce@hogranch.com>]

> Does PC host software have control over when burst transfers are
> used to address a PCI memory-mapped device or is this handled
> automatically in hardware (keying off of sequential address accesses)?  

The latter. Its transparent to the software and is keyed off of sequential
write addresses.
 
> I have a device on my board that will be mapped into the PCI memory map
> with which I would like to be able to take advantage of burst
> write transfers. The device only requires a single memory
> address decode for access (it looks like a FIFO).  If I am going to send a 
> block of data to it, does the software have to address sequential 
> addresses or can it just write to a single address and get the timing
> benefit of the burst mode transfer?

A burst by definition increments the destination address.  I'd suggest you
decode your FIFO into, say, a 4k or 8k block so that you can use REP MOVSD or
similar techniques to write to it.  In fact, this is what most graphics
accelerators do for the data port that writes thru the bitblt engine...

-jrp
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