Re: Burst Write Transfers from PC Host's Perspective

[Dave New <den@aisinc.com>]

Brian Carlson wrote:
> 
> Hello,
> 
> Does PC host software have control over when burst transfers are
> used to address a PCI memory-mapped device or is this handled
> automatically in hardware (keying off of sequential address accesses)?
> 
> I have a device on my board that will be mapped into the PCI memory map
> with which I would like to be able to take advantage of burst
> write transfers. The device only requires a single memory
> address decode for access (it looks like a FIFO).  If I am going to send a
> block of data to it, does the software have to address sequential
> addresses or can it just write to a single address and get the timing
> benefit of the burst mode transfer?
> 
> Thanks,
> Brian
> --

Oh boy, did you ever ask the $64K question, Brian.  It turns out that
an "overlooked" (IMHO) missing feature of PCI is that it does not
support single-address bursts.  This is because the target device
can interrupt the transfer at any time during the burst, and then
the master must retry the remainder of the transfer sometime later,
with an updated address corresponding to whatever the next sequential
address would have been.  The workaround is to not fully decode your
FIFO address.  For instance, if you need to handle up to 1 Mbyte
transfers without worrying about checking for address wrapping, then
fix it so your FIFO is accessible over a 1 Mbyte address range.  Then,
any access in that area will feed your FIFO.  This, of course,
disallows any "continuous" DMA solutions, where the maximum length
of the DMA transfer is essentially infinite.  An alternate is
to arrange "privately" between your master and target to not
increment the target address on retries.  This would require a
custom master, as I'm not aware of any off-the-shelf chipsets
that support that (not even in I/O space, for cryin' out loud 8-).

Beyond that, if the host-to-PCI bridge is mastering the transfer,
you will likely get write bursts to your target (given that you
have implemented the workaround) if the CPU speed is faster than
the PCI bus transaction time, and the bridge chip will combine
sequential writes into bursts (most modern chipsets do).  If your
CPU is mastering reads, though, don't expect any bursts unless
your target device is marked cacheable and prefetchable.  The solution
there is to implement bus mastering on your device.  If it's the
data source, it tends to make more sense, anyway.  For instance,
a video frame grabber will master the bus, thus producing burst
writes into the CPU memory or the video display board (given that
most modern CPU chipsets and display boards allow this).

-- 

Cheers,

DaveN
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