interrupt latency...

["Jasper Balraj" <jasper@utopia.hclt.com>]

Hello!

I'd like to know the exact way to calculate the interrupt latency
in PCI bus. I understand, since the interrupt pins at the PCI connectors
are shared, when there's an interrupt, the device driver has to read
from the device's status register and check whether that device is the
source of interrupt. If that device had not generated the interrupt, pass 
control to the previous device driver. So while calculating the interrupt
latency, am I right that one has to take into account all this PCI bus reads,
compare and jump instructions (for the worst case)? Is there any typical
interrupt latency period value for the PCI bus? Why I am asking this is
I am planning to have a 8 DWORD FIFO in my PCI controller. So after 
filling-up the FIFO, my on-board processor would generate an interrupt in 
the PCI bus to tell the host to put my PCI controller in the initiator
mode and do bus master xfer directly to the host memory. According to 
my data xfer rates, my add-on processor may interrupt the host, some
4000 times in a second to transfer 8 DWORDS of data each time thru' the
FIFO. So the total time wasted because of interrupt latency itself, in 
a second, itself  will be 4000 times that of a single interrupt. Will 
this create any problem with other PCI cards like graphics adapters,
PCI-SCSI, or so.
 
I'll be really glad to get any info. in this regard. Thanx in advance.

-Jasper

jasper@hclt.com
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