Re: interrupt latency...

[Dave New <den@aisinc.com>]

Jasper Balraj wrote:
> 
> Hello!
> 
> I'd like to know the exact way to calculate the interrupt latency
> in PCI bus. I understand, since the interrupt pins at the PCI
> connectors are shared, when there's an interrupt, the device driver
> has to read from the device's status register and check whether that
> device is the source of interrupt. If that device had not generated
> the interrupt, pass control to the previous device driver. So while
> calculating the interrupt latency, am I right that one has to take
> into account all this PCI bus reads, compare and jump instructions
> (for the worst case)?

Yes.

> Is there any typical interrupt latency period
> value for the PCI bus?
You're not really interested in 'typical'.  If you don't want to
drop any data, you need worst case.  This number is dependent
on the speed and load of the CPU, and other masters running on
the bus.

> Why I am asking this is I am planning to have
> a 8 DWORD FIFO in my PCI controller. So after filling-up the FIFO, my
> on-board processor would generate an interrupt in the PCI bus to tell
> the host to put my PCI controller in the initiator mode and do bus
> master xfer directly to the host memory.

Rather than having your board interrupt the processor every time
it wants to move 8 DWORDS, you should build something similar to
a scatter/gatter DMA engine capability into your board.  Program
it for a series of transfers, up to some larger block size.  Then
you can take the load off of the CPU for interupt processing.  Your
major worry then will be what is the maximum bus mastering latency
on the PCI bus.  This is dependent on the arbiter algorithm and
the behavior of other boards plugged in with you.  A good systems
queueing theory modeling program may help you there.  As far as I
know, no one vends an off-the-shelf package for such an analysis
for the PCI bus (but there ought to be) that takes into account
popular host chipsets and video, etc. boards.  One company vends
a Rate Monotonic Analysis package for interrupts, which has some
built in numbers for interrupt rates for popular adapters, but it
assumes no bus latency, and it's a pricey package (IMHO), given
that RMA is nothing more than a arithmetic series calculation.
There are published papers from the SEI on RMA.  It's mostly
good for fixed-priority schemes, where a CPU is hooked to a
set of devices all on different fixed priority interrupt lines,
although some research has been done on adapting it to other
situations.

> According to my data xfer
> rates, my add-on processor may interrupt the host, some 4000 times in
> a second to transfer 8 DWORDS of data each time thru' the FIFO. So the
> total time wasted because of interrupt latency itself, in a second,
> itself  will be 4000 times that of a single interrupt. Will this
> create any problem with other PCI cards like graphics adapters,
> PCI-SCSI, or so.
> 

Anything that interrupts the CPU at 4 KHz is likely to impact other
system resources.  You will have to decide if the perceived slowness
seen by the user is OK.  If your interrupt routines are really tight,
you might impact the system somewhat less than 10%.

> I'll be really glad to get any info. in this regard. Thanx in advance.
> 
> -Jasper
> 
> jasper@hclt.com

-- 

Cheers,

DaveN
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
Dave New, den@aisinc.com    | Machine vision?
Applied Intelligent Systems |      I'm glad *they* can see the future...
3980 Ranchero Drive         | 
Ann Arbor, MI  48108        | Opinions expressed are mine.    | PGP 2.6
(313) 332-7010       | 08 12 9F AF 5B 3E B2 9B  6F DC 66 5A 41 0B AB 29
(313) 332-7077 FAX
š,