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Re: bad PCI cycles
Vrover@aol.com writes:
> We are trying to track down a PCI bus crash and have found what appears to be
> an illegal PCI bus state.
>
> With our logic analyzer, we have seen a condition where FRAME and IRDY are
> asserted for one cycle each. This would be fine except they are both asserted
> for the SAME cycle. This appears to be illegal.
>
> Does anyone know of improper PCI bus behavior by any of the NCR 53C810/25
> series controllers or DEC 21x4x ethernet controllers?
You didn't ask about Weitek, but here goes:
I have seen illegal behavior from the Weitek P9100. In a previous
life, I designed a R4600-PCI bridge (in an Altera Max7000 EPLD) and I
found that the P9100 would assert TRDY two clocks after FRAME and then
disconnect, with total disregard of the IRDY signal. I managed to
work around this problem by waiting until I had data available in the
bridge.
I reported the problem to Weitek, but never heard a word from them on
this.
Kai
--
Kai Harrekilde-Petersen <khp@dolphinics.no> #include <std/disclaimer.h>
http://www.dolphinics.no/~khp/ Linux: the choice of a GNU generation
"Argue for your limitations, and sure enough - they're yours" --Richard Bach.
Πy