No Subject

["Luc Baticle" <baticle1@InfoRoute.CGS.Fr>]

In the PCI specification 2.1 page 138 section 4.3.1 the maximum
allowable skew between two components is defined as 2 ns. The
figure page 139 confirm this statement.

On page 30 of the CompactPCI specification 1.0 section 3.3 it is
written : " A maximum skew of 2 ns is allowed in the system at 33
MHz between any PCI devices at the clock input of the integrated
circuits ". This is consistent with the above sentences.

It is also stated at page 32 section 3.3.2.2 that : " The onboard
clock signals of a system board should be delayed beyond the clocks
routed to the backplane by 3.8 ns +/- 400 ps to accommodate best
and worst case backplane skews ".

In the worst case if we have an adapter in slot 1 and a system
board in slot 0, we will have about 495 ps delay between the system
slot CPU and the adapter. This is calculate using 190 ps/inch trace
as specified in the PCI specification 2.1 page 155 section 4.4.3.3
with a trace length of .8 inch (1 slot) + 2.5 inch (adapter board
clock trace) = 3.3 inch ; 3.3 * 190 = 627 ps.

So the 2 ns maximum skew specified above by PCI and CompactPCI is not
respected because 3.8 ns (system slot delay) - 627 ps (first slot
delay) ~= 3.1 ns > 2 ns (maximum skew between component).

In the best case the last slot 7 used with a maximum delay of 1.2 ns
page 31 section 3.3.2 CompactPCI 1.0, we still have a problem :
3.8 ns (system slot delay) - 1.2 ns (first slot delay) - 2.5 * 190 ps
(adapter board clock delay) ~=  2.1 ns > 2 ns (maximum skew between
component).

Can anyone explain this onboard 3.8 ns delay, thank you in advance.

Laurent Bernard
Design Engineer
Micro Process Ingenierie
97bis, rue de Colombes
92405 COURBEVOIE CEDEX
FRANCE
Tel: +33 1 47 68 80 80
Fax: +33 1 47 88 97 85
¼ÜÉ