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Re: PCI Trace Velocity
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Re: PCI Trace Velocity
- From: Andy Ingraham <ingraham@wrksys.ENET.dec.com>
- Date: Mon, 30 Dec 96 10:26:49 EST
- Apparently-To: pci-sig@znyx.com
- Cc: ingraham@wrksys.ENET.dec.com
- Resent-Date: Mon, 30 Dec 96 10:26:49 EST
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"RgD3l3.0.xn3.J1-no"@dart>
- Resent-Sender: pci-sig-request@znyx.com
I think the PCI's spec of 150-190 ps/inch is mainly meant to control
PCI clock skew.
Clock lines on PCI cards are supposed to be 2.5 +/- 0.1 inch long. At
150-190 ps/in, the raw (unloaded) etch delay would be 427 ps +/- 67 ps.
Of this 67 ps variation, 17 ps comes from the 0.1 inch etch length
tolerance, and the other 50 ps is due to the 150-190 ps/in raw trace
velocity range. On top of this are a whole slew of other effects
(IC input capacitance, bends in the etch, etc.), not to mention the
clock driver, which is why the tolerance seems so tight.
The formula (1.017 * sqrt(0.475 * Er + 0.67) ) is based on pure
microstrip without any soldermask, the green coating usually applied
over everything except pads and pins. The addition of soldermask
decreases the trace velocity (increases the ps/inch).
Regards,
Andy Ingraham
½ ø