Re: 3.8 ns delay on CompactPCI clock

[Andy Ingraham <ingraham@wrksys.ENET.dec.com>]

I am not familiar with the CompactPCI spec, but I'll make some
guesses.  (There don't seem to be many CompactPCI experts here; there
tend to be more questions than answers.)

I would assume that the clocks are routed on the backplane with equal
length etch to all slots.  If not, one would have a rather tough time
achieving the 2 ns clock skew spec just across the adapter boards in
slots 1 through 8, let alone the system board in slot 0.

If the system board in slot 0 is responsible for distributing clocks
to all other slots, and the backplane is passive, then the trace to
slot 1 must be lengthened to *at least* 6.4 inches, the shortest
length to reach slot 8.

If the system board uses its own clock rather than picking it off the
backplane like the other slots, then some compensation is necessary
for the lack of this 6.4+ inch trace and two connectors.

If a backplane clock fanout IC is involved, then there is even more
reason to add delay in the system board, to compensate for the clock
delay to all the other non-system cards.

Regards,
Andy Ingraham
¿8(