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Help! AMCC S5933Q Compatibility Issue

“Why can’t we all just get along?”
                                           -- Rodney King

Dear PCI-SIG Mailing List Recipients,

I am baffled by a problem that, hopefully, someone in this sig has dealt
with regarding the AMCC S5933QB Matchmaker PCI I/F chip. I have designed
a board using the chip and it works great -- as long as I don’t want to
run anything but the DOS based test program that interacts with it. For
example, during boot, the network protocol stack for my ISA 3Com
ethernet board gets loaded, but it doesn’t detect any devices attached
to the network. And, when I try to run Win 3.1, most of the time (see
below) the computer locks up with the display going to power down mode
(ie. the H and V syncs go away). 

“Ah, you say, something in the expansion ROM has gone awry...” Well, if
I fill the EEPROM with 0xFF and cycle the power (which the AMCC chip
should interpret as "no ROM present"), I still have the network problem,
but Win 3.1 boots! I've removed all cards from the Intel Endeavor P150
motherboard except the NIC, Diamond Stealth 64 VRAM PCI SVGA and my
custom PCI board, as well as juggling the slots where the cards are
plugged in. I’ve tried numerous permutations of the expansion ROM
contents, but they all produce identical results. One version has the
Init size of 0x00 and the Init code entry point of 0x00 0x00 0x00. The
other has an Init size of 0x01 and an Init code entry point of 0xCB 0x00
0x00, which should be a "far ret" instruction. I've also played with the
"min_grant" and "max_lat" locations and tried different vendor/device
ID's to no effect. I’ve included the entire contents of the EEPROM below
so there won’t be any confusion.

Anybody got any clues? Many thanks in advance for your help!

P.S. The Macintosh image works great. Let's hear it for FCode! And I did
try an expansion ROM with just the PC image just in case my PC was
Macophobic. No change.

Regards,

Ken Crocker, Principal Engineer
Ken Crocker Consulting
e-mail: kcrocker@kcconsulting.com
(619) 457-0340 Voice, Voicemail, Fax, Modem (autoswitch)


EEPROM Expansion "ROM" images follow. "//" signifies a comment. Bytes
are laid down in the order listed (ie. no endian conversion). All
locations not specified are set to 0x00.

//==============================================================================
// Start of ROM image #0 (IBM-PC)
00: 55 AA           // Signature bytes (IBM-PC)
02: 00              // Initialization size (0 x 512 bytes)
//02: 01            // Initialization size (1 x 512 bytes)
03: 00 00 00        // INIT function entry point. No code since init
size is 0.
//03: CB 00 00      // INIT function entry point. "far ret" instruction.
06: 00 00           // Reserved
08: 00 00 00 00     // Reserved
0C: 00 00 00 00     // Reserved
10: 00 00 00 00     // Reserved
14: 00 00 00 00     // Reserved
18: 20 00           // 2-byte pointer to PCI Data Structure

// Start of PCI data structure
20: 50 43 49 52     // Signature field (ASCII string 'PCIR')
24: E8 10           // Vendor ID
26: 50 47           // Device ID
28: 00 00           // Pointer to Vital Product Data
2A: 18 00           // PCI data structure length (starts with signature
field)
2C: 00              // PCI data structure revision (=0 for this
definition)
2D: 00 00 FF        // Class code (undefined device)
30: 01 00           // ROM Image length (in 512 byte units)
32: 00 00           // ROM Image Revision level
34: 00              // Code type (Intel x86, PC-AT compatible)
35: 00              // Indicator (bit D7=1 signifies "last image")
36: 00 00           // Reserved

// Boot load image for the S5933 Controller's PCI Configuration Reg
40: E8 10           // Vendor ID
42: 50 47           // Device ID
44: 00              // Not used
45: C1              // Bus Mstr config (Mstr from PCI, Rd async, Wr sync
FIFO's)
46: 00 00           // Not used
48: 00              // Revision ID
49: 00 00 FF        // Class code (undefined device)
4C: 00              // Not used
4D: 00              // Latency timer
4E: 00              // Header type
4F: 00              // Self test (no BIST support)
50: C0              // PCI Operation Regs in mem addr space
51: FF              // Required by S5933Q
52: E8              // Required by S5933Q
53: 10              // Required by S5933Q
54: E0 FF FF FF     // Base address #1 (mem addr space, 32 bytes / 8
DWORDS)
58: 00 00 E0 FF     // Base address #2 (mem addr space, 2 MBytes)
5C: 08 00 00 FF     // Base address #3 (mem addr space, 16 MBytes,
prefetchable)
60: 08 00 00 FF     // Base address #4 (mem addr space, 16 MBytes,
prefetchable)
64: 00 00 00 00     // Base address #5
68: 00 00 00 00     // Not used
6C: 00 00 00 00     // Not used
70: 01 F8 FF FF     // Expansion ROM base address (2K bytes / 512
DWORDS)
74: 00 00 00 00     // Not used
78: 00 00 00 00     // Not used
7C: FF              // Interrupt line ("unknown" or "no connection")
7D: 01              // Interrupt pin (PCI "INTA#" could be used)
7E: 00              // Min grant (non-critical)
//7E: 0A            // Min grant (10 * 250ns = 2.5us)
7F: 00              // Max lat in 250ns units (non-critical)
//7F: 1F            // Max lat in 250ns units
                    // (0x1F << 3 == 0xF8, the value to be put in
LatTimer reg)

// Byte checksum of "initialization block" for image #0
1FF: <000-1FE>      // Computed checksum of provided range

//==============================================================================
// Start of ROM image #1 (Macintosh)
200: 55 AA          // signature bytes
202: 40 00          // 2-byte offset to FCode program
204: 00 00 00 00    // Reserved
208: 00 00 00 00    // Reserved
20C: 00 00 00 00    // Reserved
210: 00 00 00 00    // Reserved
214: 00 00 00 00    // Reserved
218: 20 00          // 2-byte pointer to PCI Data Structure

// Start of PCI data structure (32-bit aligned)
220: 50 43 49 52    // Signature field (ASCII string 'PCIR')
224: E8 10          // Vendor ID
226: 50 47          // Device ID
228: 00 00          // Pointer to Vital Product Data
22A: 18 00          // PCI data structure length (starts with signature
field)
22C: 00             // PCI data structure revision (=0 for this
definition)
22D: 00 00 FF       // Class code (undefined device)
230: 01 00          // ROM Image length (in 512 byte units)
232: 00 00          // ROM Image Revision level
234: 01             // Code type (OpenBoot standard for PCI)
235: 80             // Indicator (bit D7=1 signifies "last image")
236: 00 00          // Reserved

// FCode starts here
240: @40            // This cryptic command opens binary file
"FCode.out" and
                    // copies FCode information starting at offset 0x40

// End of Expansion ROM Image
Áü