pci

[Breck Ricketts <breck@sound.net>]

I have a question about a general 'memory write' cycle on a PENT 133.

I am WRITING data to the PCI bus at location $c0000000 (using C code and
a simple VXD)

everything works just fine except for a few transactions per 10000:
FRAME is asserted, C/BE0,1,2,3  indicate a MEMORY WRITE phase, and then
the problem
occurs IDSEL is asserted at the first rising edge of CLK after assertion
of FRAME.
during this time the DATA is incorrect.  WHATS the deal

any help would be appreciated.

Thanks 
Breck Ricketts
Instant Access Imaging
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