pci

[scaramouche@vnet.IBM.COM]

*** Reply to note of 01/03/97 17:09
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From: Bill Zevin
Subject: pci

Breck, if all you are doing is memory write (CB/E#=7), then IDSEL# is
not pertinent.  IDSEL# is only valid for configuration cycles
(CB/E#=x'A' or x'B') and only valid during the Address phase.

IDSEL# has no definition during a DATA phase.

What are you qualifying DATA with?  It should only be when TRDY# and
IRDY# are both active.

IDSEL# is most likely one of the upper A/D lines, although there is no
formal recommendation given by the specification.

Regards,
Bill Zevin
IBM Networking Hardware Division

** referenced post:

I have a question about a general 'memory write' cycle on a PENT 133.

I am WRITING data to the PCI bus at location $c0000000 (using C code and
a simple VXD)

everything works just fine except for a few transactions per 10000:
FRAME is asserted, C/BE0,1,2,3  indicate a MEMORY WRITE phase, and then
the problem
occurs IDSEL is asserted at the first rising edge of CLK after assertion
of FRAME.
during this time the DATA is incorrect.  WHATS the deal

Thanks
Breck Ricketts
Instant Access Imaging

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From The Desk Of BILLYZ...
scaramouche@vnet.ibm.com
IBM Networking Hardware Division
ÆD3