Questions involving main<->PCI bus interactions.

[Randy Smith <randys@osf.org>]

    Greetings!  I have a couple of questions about the PCI bus that I
  was hoping folks could help me with--I've looked through the PCI
  spec (rev 2.1) and haven't figured out the answers.  Specifically:
	*) Do accesses from an I/O processor on the PCI bus to main
	   memory respect the main (application) processors cache?
	*) If you think of a processor on the system bus and the
	   processor on the PCI bus in an SMP context (i.e. if you are
	   running programs on both of them and communicating through
	   memory), what is the consistency model of the interaction
	   between the two?  Can it be described by any of the
	   standard terms (sequentially consistent, processor
	   consistent, or weakly consistent)?  I think Appendix E
	   attempts to explain this, but I had a hard time translating
	   it into concepts that map well to an SMP programming model.
	*) If a processor on the PCI bus does a word (32 bit) access
	   to main memory, is that access atomic WRT accesses by the
	   applications processor?  What's the largest access that is
	   atomic?  (I suspect the answer to this question is either
	   "aligned doubleword (64 bits)" or "byte").

    For those that are interested, we're working on a communications
  system based on remote memory access through communications
  co-processors on the PCI bus.  We program the communications
  processor to do operations based on incoming packets.  I need to
  know the details of the memory consistency to program that processor
  correctly.  Thanks much in advance for any help.

					-- Randy Smith
					Programmer, OSF

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