DEC 21150 Secondary PCI Bus Clk Route Conflict w/ CPCI

[Terry Trausch <TTrausch@msmail.radisys.com>]

I'm using a DEC 21150 PCI-PCI bridge and am routing the secondary PCI bus a 
CompactPCI connector.  In doing so, I've run across a problem that I was 
wondering if anyone had either experienced before or had any ideas on.

The CompactPCI spec rev 1.0 says:
"3.3.2.2 Clock routing to local PCI peripherals
Any onboard PCI peripherals, including PCI-PCI bridges, must be provided a 
clock that is delayed to accomodate the max. prop. delay of the backplane 
clocks and still meet the 2ns overall skew requirement.  Up to 800ps of skew 
is allowed for onboard clock distribution (including the clock buffer 
internal skew).  The onboard clock signals should be delayed beyond the 
clocks routed to the backplane by
3.8ns +/- 400ps to accomodate best/worst case backplane skews."

The DEC 21150 primary PCI bus clock and secondary PCI bus clocks are 
synchronous.  It produces it's own set of secondary PCI bus clocks and uses 
one of these clocks (externally wrapped around to the input) for the input 
secondary PCI bus clock.  However the DEC 21150 bridge data sheet says:
"11.1 The max. skew between p_clk and s_clk rising/falling edges is 7ns 
[with a min. skew of 0ns].
11.2 The output secondary PCI bus clock edges are delayed from the primary 
bus clock edges by a min. of 0 to a max. of 5ns.  The max. skew is 500ps. 
 Therefore to meet the primary to secondary clock requirements stated in 
11.1, no more than 2ns of delay is allowed for secondary clock trace 
returning to the device secondary clock input."

Any suggestions on how to meet the 3.8ns CPCI spec and the 2.0ns DEC bridge 
spec?  Any CPCI designers dealt with this already?
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