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PCI Trend (fwd)

> We have a requirement of 'high'
> data through-put rate on the PCI 
> bus, ranging from 50 - 100+ MBytes/sec.
> In order to ensure that this chip
> will fit well in the commerically 
> available technologies (e.g. workstations,
> chip sets, etc.) in the time frame of
> introduction (~ mid '98), we would
> like to get as much feed back from
> the PCI community as possible to see what
> roadmap of the PCI bus will
> look like in this timeframe.
> We have the following questions and
> would love to get some feedback from you.

I will not answer each of the four questions individually.
I also do not speak on behalf of Compaq.  I merely present
my opinions of the mainstream chipset/system market.

The mainstream PCI bus that will be found in most system
will be 33 MHz, 32-bit, 5V.  Note that the 5V may be misleading.
Many chipsets available today really drive 3.3V outputs but
are 5V tolerant and meet the 5V AC timing requirements.
There may be a shift in the future to true 3.3V systems
as 5V tolerance becomes more difficult.  However, this
would make all the 5V add-in cards available today

Your need for 50 - 100+ MBytes/sec. is very aggressive
on the PCI bus.  While the PCI bus can sustain transfer
rates up to around 100 MB/sec (not much over 100), that
is shared among all devices on the primary pci bus.
I would highly recommend that you look into your bandwidth
requirements and see if they can be lowered.  Otherwise
you may limit your design to only working in the few
systems that have higher bandwidth (66 MHz and/or 64-bit)
PCI busses.
Allan Lester
ASIC Design Engineer
Compaq Computer Corp	INTERNET: lester@twisto.compaq.com
(281) 514-1899		

"The views expressed here are my own, and not those of my employer."