Re: PCI Clock Specs and PLL

[Ivor Bowden <ivor@peritek.com>]

This subject was discussed quite a bit here a while back. You can check the
archives for more information.

I think the conclusion was you can not use a PLL type chip for buffering the
clock and still be compliant with the PCI spec. Some manufacturers modulate
the clock to reduce EMI. 

You can use a fast buffer.

The IDT 74FCT807CT is a 1:10 clock driver with tpd of
1.3 nS (min) to 2.5 nS (max) into 50 ohm 10 pF load.

The Micro Linear ML65244 is a dual quad buffer/line driver with a
tpd of 1.3nS (min) to 1.5nS (max) into a 500 ohm 50 pF lead.

If the clock and data/control buffers have the same prop delay, the timing
is preserved. On the same note, you can adjust the tsu/th timing by using
buffers with different tpds for clock and data/control, at the expense of
cycle time.

At 10:24 AM 1/22/97 -0800, you wrote:
>Hello PCI Community,
>
>PCI clock specs allow changing (and stopping) 
>of PCI clock.  We are considering using the
>PCI clock to drive our ASIC (for synchronization
>benefits).  To control internal clock skew, we also 
>want to include an on-chip PLL.
>
>But PLL won't work well with a reference clock
>that could be changing.  Does anyone have any
>good solutions for this problem?
>
>Or is it the case that people are ignoring this specs
>and usually support only some fixed frequencies?
>
>Since our application is not in the portable environment,
>is it safe to assume that stopping or changing the clock
>is not very common?  Who are doing this today in
>their systems?
>
>Thanks in advance for your help and feedback.
>
>- Ben -
>
>_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/
>  Benson Cheung           (bcheung@adobe.com)
>  Adobe Systems Inc.
>  Printing & Systems Division
>  M/S  P05
>  303 Almaden Blvd.
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>
>
-Ivor

--------------------
standard disclaimer:
I speak for myself and my views may not be the same as my employer's.
Ivor Bowden
Peritek Corp
phone: (510) 531-6500
FAX: (510) 530-8563
email: ivor@peritek.com
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