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PCI Clock Specs and PLL
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: PCI Clock Specs and PLL
- From: Benson Cheung <bcheung@Adobe.COM>
- Date: Wed, 22 Jan 1997 10:24:57 -0800
- Resent-Date: Wed, 22 Jan 1997 10:24:57 -0800
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"6jL0u1.0.b53.Djbvo"@dart>
- Resent-Sender: pci-sig-request@znyx.com
Hello PCI Community,
PCI clock specs allow changing (and stopping)
of PCI clock. We are considering using the
PCI clock to drive our ASIC (for synchronization
benefits). To control internal clock skew, we also
want to include an on-chip PLL.
But PLL won't work well with a reference clock
that could be changing. Does anyone have any
good solutions for this problem?
Or is it the case that people are ignoring this specs
and usually support only some fixed frequencies?
Since our application is not in the portable environment,
is it safe to assume that stopping or changing the clock
is not very common? Who are doing this today in
their systems?
Thanks in advance for your help and feedback.
- Ben -
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Benson Cheung (bcheung@adobe.com)
Adobe Systems Inc.
Printing & Systems Division
M/S P05
303 Almaden Blvd.
San Jose, CA 95110-2702
(408) 536-2872 (408) 537-8411 (FAX)
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¸ §