Clock Timing Specification: Spec 2.0 vice versa Spec2.1

[Holger.Kuefner@FernUni-Hagen.de (Holger Kuefner)]

Hello PCI Community,

I developed a PCI master/target controller with an FPGA. To get a fast one
and to solve timing problems I used a couple of state machines which are clocked
on positice clock edge and some which are clocked on negative clock edge. So in  
this case it`s important to know the minimum time the clock is High and the 
minimum time the clock is Low to achieve a correct and reliable "teamwork" of 
all state machines and additional logic.

Now in Spec 2.0 (4.2.3.1, table 4-5, p. 97) a Clock High and Low time of 12 (!) ns 
is noted, in Spec 2.1 (4.2.3.1, table 4-5, p. 133) a Clock High and Low time of
11 (!) ns is defined.
Which value is the right one? Know anybody something about it? I don`t found
any comment about a change of this value from Spec 2.0 to Spec 2.1.
 
Thanks in advance for answering!

	Holger

================================================================================
Holger Kuefner			     Phone:  +49/2331/987-4423
University of Hagen     	     Fax:    +49/2331/64373
Technische Informatik I              E-Mail: holger.kuefner@fernuni-hagen.de
D - 58084 HAGEN
GERMANY
================================================================================
œŠ