Re: Clock Timing Specification: Spec 2.0 vice versa Spec2.1

[Andy Ingraham 24-Jan-1997 1328 <ingraham@wrksys.ENET.dec.com>]

> Now in Spec 2.0 (4.2.3.1, table 4-5, p. 97) a Clock High and Low time of 12 (!) ns 
> is noted, in Spec 2.1 (4.2.3.1, table 4-5, p. 133) a Clock High and Low time of
> 11 (!) ns is defined.
> Which value is the right one?

The value in revision 2.1 (11 ns) is correct, if you want to be
compliant to that revision of the PCI spec.

>                               Know anybody something about it? I don`t found
> any comment about a change of this value from Spec 2.0 to Spec 2.1.
 
There is no place where all the changes from revision 2.0 to 2.1 were
documented.  The final revision 2.1 spec doesn't have "change bars".

The folks at Intel did this change, after realizing that the original
requirement was inconsistent with the usual practices for specifying
crystal oscillators.

Most oscillators have a 60/40 duty-cycle spec, meaning that the
pulsewidth can be anywhere from 40% to 60% of the period, when
measured at some threshold voltage (typically 1.4 V for TTL
oscillators) with some test load.  40% of 30 ns is 12 ns.  That's
where the original value comes from.

However, in the PCI spec, its minimum pulsewidth is specified at 2.0 V
(for T_high) and at 0.8 V (for T_low).  See Figure 4-7 on page 132. 
The PCI SIG forgot to take that into account when they wrote the spec.

To accommodate the non-zero rise- and fall-times of the clock, the
spec was changed from 12 to 11 ns.  It probably should have been
changed further, to perhaps 10 ns, so 11 ns is a compromise.  (When I
worked the numbers, I came up with 10.56 ns or less.)

This doesn't even take into account further duty-cycle impairments
caused by loading (real load vs. test load), distribution, crosstalk,
etc.  It is generally necessary to actively fan out the clock
separately to all loads, which could slice another nanosecond or so
off the pulsewidth, in a worst-case analysis.

Regards,
Andy Ingraham
ta