Re: PCI Interrupt Binding

[Ali Najafi <alinajafi@simei.aztech.com.sg>]

At 03:28 PM 1/24/97 PST, you wrote:
>
>In the PCI - PCI bridge spec 1.0, under section 11, I see that there is a 
>specified way to connect interrupts on the backplane.  However, the way it's 
>presented I can see two ways to route the interrupts on the backplane and be 
>compatible with this spec.  I'm sure I'm just misreading some part of the 
>spec and was wondering if someone could set me straight.
>
>If you look at it from the standpoint that all the interrupts are fixed on 
>the device,  I could connect INTA# from device 0 (the host -> bridge) to 
>INTB# of device 1 (the first PCI slot)  OR
>
>If you look at it from the standpoint that all the interrupts are fixed on 
>the connector, I could connect INTA# from device 0 (the host -> PCI bridge) 
>to INTD# of device 1 (the first PCI slot).
>
>Which standpoint is the correct read?  Here a text-based picture would 
>really be worth a thousand words in the spec.
>
>Terry Trausch
>terry.trausch@radisys.com
>RadiSys, Inc.
>
>

Each PCI device can have upto 4 interrupt pins. If it is a single function
device, it can have only one interrupt pin and this one pin is INTA#. A
multi-funciton pci device may use all the interrupt pins, INTA#, INTB#,
INTC# and INTD#. This naming is independent of any context: The designer of
the chip decides which pin to be called what. And this naming will not
change. When you say "INTA# pin of my chip", you always know what pin you
are talking about and you know that no matter to what INT?# pin of the
connector or of another pci device it is connected to, that pin, on your
chip, is always called INTA#.

The device numbers that you have considered (device 0, the host -> bridge
and device 1, the first PCI slot) are different from what is meant by device
numbers in Section 11 of the pci to pci bridge spec. I have described the
device numbers in this reply.

With the above in mind, the following is another presentation of devices 0
through 4 of Table 9 in Section 11 of the pci to pci bridge spec. The
followings are implied in that section:

1- The pci to pci bridge is on an add on card, and the add on card may be
   mounted on any slot
2- The primary interface of the bridge is connected to the connector
3- The add on card contains at most 32 pci devices, numbered 0 to 31
4- These devices are connected to the secondary interface of the bridge
5- Table 9 only talks about routing the interrupt pins of these devices to
the     interrupt pins of the connector and not about routing the interrupt
pins of     the bridge to the connector.
6- It is not necessary for the bridge to perform this routing

In the following presentation of Table 9, which only shows devices 0 through
4, the interrupt pins in one column belong to the device on the add on card
except for the interrupt pins in the left most column which belong to the
connector. 
The interrupt pins in one row are wired together. For instance, INTA# of 
Device 1 is wired to INTB# of Device 0 and they are wired to INTB# of the
connector.


  C
  o      D      D      D      D      D
  n      e      e      e      e      e
  n      v      v      v      v      v
  e      i      i      i      i      i
  c      c      c      c      c      c
  t      e      e      e      e      e
  o
  r      0      1      2      3      4

INTA#  INTA#  INTD#  INTC#  INTB#  INTA#

INTB#  INTB#  INTA#  INTD#  INTC#  INTB#

INTC#  INTC#  INTB#  INTA#  INTD#  INTC#

INTD#  INTD#  INTC#  INTB#  INTA#  INTD#


If the bridge itself issues an interrupt, and the bridge is a single
function pci device, it only has an INTA# interrupt pin. This pin should be
connected to INTA# of the connector.


Hope this helps.

A. Najafi
&4$