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Another Burst Question
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Another Burst Question
- From: brians@Aureal.com (Brian Sassone)
- Date: Mon, 27 Jan 1997 18:43:26 -0800 (PST)
- Resent-Date: Mon, 27 Jan 1997 18:43:26 -0800 (PST)
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"5bZnK1.0.lI1.ofMxo"@dart>
- Resent-Sender: pci-sig-request@znyx.com
If a device has marked it's memory space as non-prefetchable (BAR[0]=0),
will it still receive memory write bursts? The requirements for
prefetchable memory are stated on pp 196 of the 2.1 spec:
1) no side effects on reads
2) returns all bytes on reads regardless of byte enables
3) host bridges can merge processor writes
My device cannot tolerate 3) but needs to be able to receive bursts as the
result of write combining (pp 33) for performance reasons. Will currently
available host bridges allow this?
Brian
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Brian Sassone (brians@aureal.com) Aureal Semiconductor
Senior Design Engineer 4245 Technology Drive
510-252-4225 Fremont, California 94538
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