Re: IO and Bursting

[brians@Aureal.com (Brian Sassone)]

> > Are bursts to IO address space always forbidden on PCI?

> I suspect that you are implying that you would like to do a
> *single-address* burst to I/O space, so you can stream data
> in/out an I/O port.  

Actually, no (I already know how to fix that problem).  I'm just
wondering if I'm guaranteed that a master wont try to burst an IO 
write (cbe == 0011) to my device.  This seems to be implied by the
statements on pp34 of the 2.1 specification wrt combining and 
merging where it states:
  
  "The combining and merging of IO and Configuration transactions 
  are not allowed."

> There is nothing about doing I/O (rather than memory cycles) that would
> allow you to imply (or dis-imply) being able to do burst cycles to
> a target.  If the target allows it, it will happen.  If not, it won't.

Semantically the cycles are identical as defined in the spec.  That's 
why I'm confused by the above statement.  I'm wondering more about how 
the host bridge works.  Anybody familiar with the bridge spec who can
tell me how HBs are guaranteed to operate?

Brian

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Brian Sassone (brians@aureal.com)                Aureal Semiconductor
Senior Design Engineer                           4245 Technology Drive
510-252-4225                                     Fremont, California 94538
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