[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: IO and Bursting
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Re: IO and Bursting
- From: Timothy Hellman/PicTel <Timothy_Hellman@smtpnotes.pictel.com>
- Date: 28 Jan 97 9:23:54 EDT
- Resent-Date: 28 Jan 97 9:23:54 EDT
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"GY1PH2.0.7E3.XnWxo"@dart>
- Resent-Sender: pci-sig-request@znyx.com
> > Are bursts to IO address space always forbidden on PCI?
>Actually, no (I already know how to fix that problem). I'm just
>wondering if I'm guaranteed that a master wont try to burst an IO
>write (cbe == 0011) to my device. This seems to be implied by the
>statements on pp34 of the 2.1 specification wrt combining and
>merging where it states:
>
>"The combining and merging of IO and Configuration transactions
> are not allowed."
Why worry about it? Just have your target disconnect with data
on the first I/O cycle (simply assert STOP with TRDY).
That way, even if the master tries to do a burst it'll be forced to
break it up into single cycles. This way you don't have any
worries about how to handle the address cycle and so forth.
As has been noted before, if you want to use bursts for performance
easons you should map your registers into memory space.
A
î