Re: IO and Bursting

[sgolson@trilobyte.com (Steve Golson)]

> I'm just
> wondering if I'm guaranteed that a master wont try to burst an IO 
> write (cbe == 0011) to my device.  This seems to be implied by the
> statements on pp34 of the 2.1 specification wrt combining and 
> merging where it states:
>   
>   "The combining and merging of IO and Configuration transactions 
>   are not allowed."

However on page 25 the 2.1 spec says

  "The basic bus transfer mechanism on PCI is a burst. A burst is composed
  of an address phase and one or more data phases. PCI supports bursts in
  both memory and I/O Address Spaces."

So the spec allows bursts in memory, IO, and configuration address spaces.
Thus in this case the address spaces are treated identically, however some
differences between them include

  IO and configuration cannot use 64b bus extension
  IO and configuration cannot use combining and merging
  IO and configuration must use linear incrementing

> > There is nothing about doing I/O (rather than memory cycles) that would
> > allow you to imply (or dis-imply) being able to do burst cycles to
> > a target.  If the target allows it, it will happen.  If not, it won't.
> 
> Semantically the cycles are identical as defined in the spec.  That's 
> why I'm confused by the above statement.  I'm wondering more about how 
> the host bridge works.  Anybody familiar with the bridge spec who can
> tell me how HBs are guaranteed to operate?

I suspect that all x86 compatible host bridges will never generate IO bursts.
However I know of at least one RISC-based system that can do it.

-seg

Steve Golson / Trilobyte Systems / +1.508.369.9669 / sgolson@trilobyte.com
Consulting in: Verilog, VHDL, Synopsys, patent analysis, reverse engineering
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