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Re: Another Burst Question

Brian Sassone wrote:
> If a device has marked it's memory space as non-prefetchable (BAR[0]=0),
> will it still receive memory write bursts?  The requirements for
> prefetchable memory are stated on pp 196 of the 2.1 spec:
>   1) no side effects on reads
>   2) returns all bytes on reads regardless of byte enables
>   3) host bridges can merge processor writes
> My device cannot tolerate 3) but needs to be able to receive bursts as the
> result of write combining (pp 33) for performance reasons.  Will currently
> available host bridges allow this?
We've seen (on the logic analyzer) write bursts to a slave marked
as non-prefetchable from a Triton chipset.  I believe the distinction
lies in *merging* vs. *combining*.  The words are used (in the
document) in a careful, consistent manner, because they really
are two different things.

Now, *read* bursts are a different matter.  Don't expect the host
processor to be able to do read bursts from a slave device into
host memory.  This is a limitation of the currently available
host bridge chipsets.  You will need to have your device master
the transfer, and do PCI writes through the host bridge to host
memory, for bursting to occur.


-- DaveN