Re: On I/O and memory address space

[goudreau@dg-rtp.dg.com (Bob Goudreau)]

Ali Najafi <alinajafi@simei.aztech.com.sg> wrote:

> Second way: Make all the registers I/O mapped...
> ...
> What I like to do is to map everything to memory. This is what PCI spec has
> suggested and also seems quite natural and practical and also helps using
> the bus bandwidth efficiently. It is also OK to map evrything to I/O space

If you mean an approach that maps the control registers *only* to I/O
Space, with no equivalent BARs that allow mapping them to Memory Space
as an alternative, then I disagree that this would be OK.  There's a
statement in section 6.2.5.1 of the PCI 2.1 spec that pretty much
mandates that control registers be Memory-accessible (regardless of
whether they are *also* I/O-accessible, which is strictly optional):

	Devices should always allow control functions to be mapped into
	Memory Space.

> 3- Based on your experience and based on the available products, which one
> of the above three methods are more common (map the registers anywhere in a
> 32 bit address space, map to I/O, implement an indirect addressing scheme,
> and maybe a fourth one: map registers to memory below 1 Meg)?

Virtually none of the dozens of controllers for which I've seen specs
use any of these methods exclusively; instead, they generally use the
dual-mode approach you mention below:

> David O'Shea has described a few issues in this regard. He was suggesting
> to use both a memory mapped and an I/O mapped BAR to point to the same
> registers. 

And this is in fact the method discussed and blessed in the
"Implementation Note" in section 3.2.2 of the spec.

I've never seen a controller that had three separate I/O BARs, but as
long as you keep them to 256B apiece, I see no reason why BIOSes
should have any trouble with them.  If it's the resource consumption
issue that you're worried about (the fact that one of your cards will
eat three times the amount of I/O space used by a typical LAN or SCSI
device), then you need to take the larger issues of system
configuration into account.  How much total I/O space will be
available for *all* PCI devices on the platforms you're targeting?
How many instances of your card will typically be used in one such
system?  What other I/O Space-hungry devices do you expect to have to
coexist with on such systems?

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