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Address/Data Stepping bit



Hi there,

What is the purpose of bit 7 of the Command Registers (Wait Cycle Control)?
According to the spec, it is used to control whether or not a device
does address/data stepping.  My questions are :

1) Does the chipset use this information to adjust bus transaction behavior?
   If so, what is the difference?
2) The spec mentions that for devices that support stepping and non-stepping,
   the bit needs to be read/write.  How does that work?  Does the system
   BIOS or OS goes in write the bit?  If so, does that mean I have
   use the bit to turn on/off address/data stepping in my chip?
3) Any other information regarding address/data stepping will be appreciated.

Thanks for your help.

Wilson Yee
Xilinx, Inc.