Re: PCI and JTAG

[cjclark@intellitech.com (cjclark)]

Ferran,

In <3301E76F.565D@cnm.es> Ferran Lisa <uunet!cnm.es!ferran> writes:
>Hello,

>I am developing a PCI board based on ALTERA reconfigurable devices, and
>I'm very interested in JTAG standard for testing and configuring these
>devices from PCI.

Great!

>In revision 2.1 of the PCI specification there is a small section about
>this topic with a reference of a book called "PCI System Design Guide",
>but I haven't found any information about this book in the PCI-SIG web
>page.

I just received my PCI spec and I too saw this reference, but it was
not included with any of the pieces we ordered.  

>I would much appreciate if anybody could tell me how to get this guide.
>Any other information about JTAG and PCI will also be welcome.

I have reviewed the PCI spec and there are some issues with what the
SIG is recommending.  My goal as chair of IEEE 1149.1 (this is the
actual standard, even though some folks continue to call it JTAG after
a group of companies interested in boundary scan testing)
is to get these resolved so vendors can implement .1 on the PCI bus
in a way that people can use it.  I have dedicated a time slot at the 
next 1149.1 meeting, 3/3, to discuss the PCI's use of .1.  We will
make a formal recommendation and if the PCI-SIG is interested, then
these recommendations could get included in the next PCI spec.

Regards,
CJ
Chair, IEEE 1149.1



-- 
My email: cjclark@intellitech.com
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